The present invention relates generally to a process for polishing semiconductor wafers. In particular, the present invention provides a polishing process for producing dopant-striation-free polished semiconductor wafers.
Polished semiconductor wafers, such as silicon wafers, are typically obtained by slicing a single crystal ingot in a direction normal to the axis of the ingot to produce thin wafers, grinding the wafers to planarize their front and back surfaces, etching the planarized wafers to remove damage created by the slicing and grinding, and chemically/mechanically polishing at least one of the etched surfaces with a colloidal silica slurry and a chemical etchant to ensure the wafer has a highly reflective damage-free surface. Prior to polishing, the surface of the wafers typically exhibit surface roughness on the front surface and/or back surface of the wafer. In general, surface roughness appears as jagged irregularities and is characterized by a peak to peak distance of less than about 100 .mu.m with an amplitude or vertical distance from peak to valley of about 70 nm to about 100 nm.
To reduce the surface roughness, wafers are typically polished using a three step polishing process wherein at least one surface of the wafer is subjected to an initial rough polish to remove the low frequency roughness, an intermediate polish to further reduce the low frequency component of roughness after the initial rough polish, and finally a finish polish to reduce the high frequency roughness. In conventional three step polishing processes, three separate polishing apparatus are used to perform the rough, intermediate and finish polishing steps.
The polishing method disclosed in U.S. Pat. No. 5,571,373 improves upon conventional three-step methods discussed above, by providing a polishing method, wherein a multi-step rough polishing process is used to perform both the rough and intermediate polishing steps on one apparatus. The method disclosed in U.S. Pat. No. 5,571,373 reduces both the cost and complexity of the overall polishing process over the conventional three step polishing method.
In U.S. Pat. No. 5,571,373, the rough and intermediate polish are performed on one apparatus by mounting the wafer in a first polishing apparatus, applying a sodium stabilized colloidal silica slurry and an amine reinforce alkaline etchant, such as a solution of potassium hydroxide and ethylene diamine, to a polishing material, contacting the polishing material, sodium stabilized colloidal silica slurry and amine reinforced alkaline etchant with the surface of the wafer, discontinuing the sodium stabilized colloidal silica slurry and applying an ammonia stabilized colloidal silica slurry. The wafer is quenched with an acidic solution, water rinsed, removed from the first polishing apparatus and transferred to a second polishing apparatus for finish polishing. The wafer is then finish polished on the second polishing apparatus using an ammonia stabilized colloidal silica slurry and an amine reinforced alkaline etchant on a high nap polishing material, to produce a haze free wafer having a surface roughness characterized by a peak to peak distance of less than about 100 .mu.m and an amplitude or vertical distance from peak to valley of less than about 1 nm as measured on a 1 mm.times.1 mm scan with an optical interferometer.
Several wafers polished by the method disclosed in U.S. Pat. No. 5,571,373, while exhibiting superior surface roughness, may nevertheless exhibit dopant striations.
As schematically illustrated in FIGS. 1(a)-1(c), dopant striations differ from surface roughness in that dopant striations appear as annular surface irregularities concentrically positioned around the axis of the wafer, while surface roughness appears as jagged surface irregularities randomly distributed across the surface of the wafer.
FIG. 1(a) schematically illustrates a perfectly flat wafer in cross section wherein the front surface 1 and the back surface 2 are ideal planer surfaces, perpendicular to the axis 3 of the wafer. FIG. 1(b) schematically illustrates a wafer exhibiting roughness in cross section. Finally,
FIG. 1(c) schematically illustrates a wafer exhibiting dopant striations in cross section, wherein an ideal planer surface 4 is normal to the axis 3 of the wafer, and tangential to a valley 5 of the striations. The amplitude of the dopant striations is equal to the distance from peak 6 adjacent to valley 5 to the ideal planer surface 4 (ie. the vertical distance from peak to valley). The wavelength is equal to the distance from peak 6 of one dopant striation, to peak 7 of the immediately adjacent dopant striation. The amplitude of the dopant striations typically ranges from at least about 10 nm to at least about 100 nm from peak to valley and the wave length, or distance from the peak of one striation to the peak of the immediately adjacent striation generally ranges from about 0.5 to about 10 mm. The amplitude and the wave length may vary across the surface of the wafer.
Dopant striations can be revealed using a "Magic Mirror" inspection tool, wherein light is reflected off of the wafer surface onto an imaging device. The imaging device produces a black and white image of the reflected light with dopant striations appearing as dark concentric rings or features in the image. In general, the Magic Mirror inspection tool is capable of detecting dopant striations having an amplitude of at least about 10 nm. For example, FIG. 2 shows an image produced by a Magic Mirror inspection tool of a P.sup.+ type silicon wafer that was polished using an ethylene diamine accelerant, wherein the wafer exhibits dopant striations (ie. dark concentric rings or features). Semiconductor wafers having dopants striations with less than about 10 nm are considered to be "dopant-striation-free" as measured by the Magic Mirror inspection tool. Alternatively, dopant striations can be measured using other surface measurement devices capable of measuring the surface topology, such as an ADE SQM model CR83 surface quality monitor which is commercially available from ADE Corporation (Charlotte, S.C.).
As device technologies continue to decrease in size down to the submicron geometry, nano-topology variations in the surface of the wafer, such as dopant striations, create problems for device manufacturers, thus device manufacturers specify featureless wafers (ie. dopant-striation-free wafers as measured by the Magic Mirror inspection tool). Therefore, semiconductor wafers exhibiting dopant striations may be rejected in the final inspection which will result in yield loss.